1. Field of the Invention
The present invention relates to a circuit arrangement or a circuit means, especially a chip or component, with at least one input and at least one output, that is connected between at least one terminal of a controller or regulator, especially a microprocessor, and at least one input of an adjusting member and/or control unit to prevent a change of a preset state of the adjusting member and/or control unit during resetting of the controller or regulator, especially the microprocessor. It also relates to a method of maintaining or preventing a change of a set state of an adjusting member and/or control unit during a reset of the controller or regulator by means of a first signal controlling the controller or regulator.
2. Related Art
A buffer circuit for the output of a microprocessor is described in German Patent Document DE 197 20 191 C1. A buffer circuit is connected between an input and output of the microprocessor and an adjusting member. The buffer circuit has a comparator circuit whose input is connected to the output of the microprocessor. The comparator circuit switches between a high level and a low level that is applied to the adjusting member when a predetermined voltage level is reached at the input of the comparator circuit. The comparative circuit is preferably a Schmitt trigger. Moreover the buffer circuit includes an energy reservoir with which the input of the comparator circuit is buffered. This energy reservoir is preferably embodied as a capacitor connected parallel to the input of the comparator. The time constant of the capacitor is selected so that the voltage level during a normal voltage interruption of the power supply occurring during a starting process or an interruption of the voltage supply from the power supply does not reach the set value of the comparator circuit. Thus the momentary state of an adjusting element controlled by the microprocessor is preserved when there is an interruption in the voltage and a reset is triggered.
An additional example of this sort of circuit arrangement is described in German Patent Document DE 40 23 700 A1. The disclosed circuit for monitoring the frequency of a signal from a microprocessor contains a frequency generator, which produces a cyclic error or reset signal, when the input signal sequence has a frequency that is outside of a predetermined frequency variation range. Furthermore this circuit arrangement comprises a voltage monitoring circuit, which blocks the so-called reset or error signals from the frequency generator to the microprocessor in the presence of an unreliable operating voltage. Furthermore an error signal supplying device is described in this paper that generates a static error signal. This error signal acts as a switching signal for the frequency generator and/or as a lock-in signal for a end stage which is associated with the microprocessor.
The above-mentioned circuit arrangement is activated when an interruption or a too rapid increase in the supply voltage occurs. Thus only reset situations, which are triggered by an overvoltage or undervoltage, are considered. Other factors, such as a processor overload or an access error that activate a reset, do not activate this circuit.
Besides by switching a lock-in signal applied to the end stage that is associated with the microprocessor, only an already established state can be given, but a previously active state set up earlier in the end stage state and desired now cannot be activated.
Buffering by an energy reservoir, such as a capacitor acts only for a predetermined time interval, namely the discharge time of the capacitor, so that the state of the end stage thus cannot be maintained independently of time considerations for that reason.
The current circuitry thus operates with either a charging or discharging time constant or a timing device or a previously active state cannot be maintained at the following end stage, although a currently fixed state can be maintained.
Furthermore a flip-flop with following end stage is known for maintaining a state. Also two I/O ports of a microprocessor are required. The state to be maintained is stored in a non-volatile memory. When a reset occurs in the microprocessor the momentary state is stored. A readout of this state is also possible by a third I/O port.
An increased circuitry expense is required because of these features. Furthermore a number of I/O ports of the microprocessor are occupied by the required circuitry.
It is an object of the present invention to provide an improved circuit arrangement or device, by which a state of an adjusting device or control unit is maintained despite an arbitrarily-caused reset of the controller or regulator controlling the adjusting device or control unit.
It is also an object of the present invention to provide a simple circuit arrangement or device and/or a simple chip or component and method, which switch an occupied I/O port for an element to be controlled, whereby the circuit device or the component operates with a static level, without time limitations, which makes a readout of the state possible.
Furthermore the simple method according to the invention, when it is employed with the above-described circuit arrangement, permits complete implementation in or by means of a processor.
According to the invention the circuit arrangement for preventing a change of a preset state of a control member and/or control unit during resetting a controller or regulator thereof has at least one input and at least one output, the at least one output being connected with at least one input of the control member and/or the control unit and the at least one input of the circuit arrangement being connected with at least one terminal of the controller or regulator. The at least one output of the circuit arrangement is connected for signal feedback to the at least one terminal of the controller or the regulator and/or the at least one input of the circuit arrangement, preferably by means of a filter comprising a resistive and reactive element.
The circuit arrangement according to the invention, which is connected between a microprocessor and a peripheral device, operates so that a given peripheral device experiences no state change because of a reset that is triggered either directly by the microprocessor itself or by another integrated circuit. The peripheral device, especially an end stage, is not switched by a reset. If the end stage is switched off, it is not turned on by the reset. The resetting of a controller or adjusting device, especially a microprocessor, is designated as reset in the following. An initialization stage calls up this reset. The circuit arrangement according to the invention guarantees that a reset with subsequent initialization stage of the controller or regulator causes no state change of the peripheral device to be controlled.
Furthermore after turning on the control device, especially in the initialization stage and/or during the power-on-reset, the peripheral device takes a definite, previously given state or maintains a previously set state.
The circuit arrangement according to the invention operates in this manner regardless of the origin of the reset. Thus for example when there is a reset that is triggered because of processor overload or an access error the circuit arrangement according to the invention operates in the claimed manner described above, as it does when the reset is caused by an undervoltage or overvoltage.
In contrast to the above-named state of the art the circuit arrangement according to the invention operates with a static level, without charging or discharging constants or timing elements.
An additional advantage of the circuit arrangement according to the invention claimed in the main claim appended hereinbelow in comparison to the large scale comparator arrangements described is that the circuit arrangement according to the invention is clearly simpler. Thus considerable cost savings and a greater reliability due to a reduced failure probability result because of the use of a reduced number of components.
The circuit arrangement according to the invention persists in its state until the microprocessor or microcontroller is reset because of the absence of the timing conditions or devices in the circuit arrangement according to the invention, and the active control by means of the operation or the peripheral device is again observed. Because of that feature the state or status of the peripheral element can be readout at any time by means of the same I/O port of the microprocessor.
According to the invention the method for preventing a change of a preset state of a control member and/or control unit during resetting a controller or regulator controlling the control member and/or control unit by means of a first signal includes the steps of:
a) forming a second signal according to the first signal from a first circuit arrangement and/or a first component;
b) controlling the control member and/or control unit with the second signal instead of the first signal; and
c) feeding the second signal back to the controller or regulator and/or together with the first signal to the first circuit arrangement and/or the first component.
Alternative embodiments of the method are possible in which a third signal is formed from the second signal and fed together with the first signal directly to the first circuit arrangement and/or first component or in which a fourth signal is formed from the third signal by means of a second component and/or a second circuit arrangement and is fed back to the first circuit arrangement and/or the first component together with the first signal.